UCS-CPU-E5-4610D - Cisco 1.70GHz 6.4 GT/s QPI 25MB Cache Socket FCLGA2011 Intel Xeon E5-4610 v3 10 Core Processor
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Cisco Xeon E5-4610 v3 (25M Cache, 1.70 GHz) processor 1.7 GHz 25 MB L3
Xeon E5-4610 v3 (25M Cache, 1.70 GHz)
- Intel Xeon E5 v3 E5-4610V3 1.7 GHz
- 25 MB L3 LGA 2011 (Socket R)
- Processor cores: 10 22 nm 64-bit 105 W
- Maximum internal memory supported by processor: 768 GB DDR4-SDRAM
About Cisco Xeon E5-4610 v3 (25M Cache, 1.70 GHz), Intel Xeon E5 v3, LGA 2011 (Socket R), 22 nm, E5-4610V3, 1.7 GHz, 64-bit
Cisco Xeon E5-4610 v3 (25M Cache, 1.70 GHz). Processor family: Intel Xeon E5 v3, Processor socket: LGA 2011 (Socket R), Processor lithography: 22 nm. Memory channels: Quad-channel, Maximum internal memory supported by processor: 768 GB, Memory types supported by processor: DDR4-SDRAM. Market segment: Server, PCI Express configurations: 1x16, 1x4, 1x8, Supported instruction sets: AVX 2.0. Processor package size: 52.5 mm. Intel® Virtualization Technology (Intel® VT): VT-x, VT-d, Maximum internal memory: 786432 MB, Cache memory: 25 MB
Intel® Hyper-Threading Technology (Intel® HT Technology) delivers two processing threads per physical core. Highly threaded applications can get more work done in parallel, completing tasks sooner.Intel® VT-x with Extended Page Tables (EPT), also known as Second Level Address Translation (SLAT), provides acceleration for memory intensive virtualized applications. Extended Page Tables in Intel® Virtualization Technology platforms reduces the memory and power overhead costs and increases battery life through hardware optimization of page table management.
Enhanced Intel SpeedStep® Technology is an advanced means of enabling high performance while meeting the power-conservation needs of mobile systems. Conventional Intel SpeedStep® Technology switches both voltage and frequency in tandem between high and low levels in response to processor load. Enhanced Intel SpeedStep® Technology builds upon that architecture using design strategies such as Separation between Voltage and Frequency Changes, and Clock Partitioning and Recovery.
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